GAMMA Research Group

Rethink Analog IC Design -- from Techniques to Tools

Publication

Journal

  1. Xitie Zhang, Evren F. Arkan, Coskun Tekes, M. Sait Kilinc, Tzu-Han Wang, F. Levent Degertekin, Shaolan Li,  “A 1.11 mm2 IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming at 40 MHz,” in IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), in press
  2. Tian Xie, Shimeng Yu, Shaolan Li, “A High-Parallelism RRAM-Based Compute-In-Memory Macro with Intrinsic Impedance Boosting and In-ADC Computing,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 9, no. 1, pp. 38-46, June 2023.
  3. Jae Hur, Yuan-Chun Luo, Tzu-Han Wang, Anni Lu, Shaolan Li, Asif I. Khan, Shimeng Yu, “Non-Volatile Capacitive Crossbar Array for In-Memory Computing,” in Advanced Intelligent Systems, vol.4, no.8, p.2100258, 2022
  4. Tian Xie*, Tzu-han Wang*, Zhe Liu, Shaolan Li, “An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique,”, IEEE Journal of Solid-State Circuits (ISSCC invited submission), vol. 57, no. 12, pp. 3804-3815, Dec. 2022. *Equal contribution
  5. Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun “Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 69, no. 6, pp. 2249-2262
  6. Lu Jie; Xiyuan Tang; Jiaxin Liu; Linxiao Shen; Shaolan Li; Nan Sun; Michael P. Flynn, “An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier,” IEEE Open Journal of Solid-State Circuits (OJSSC), vol. 1, pp. 149-161, 2021.
  7. Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, Shaolan Li, “A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure with Hardware-Reusing kT/C Noise Cancellation,” IEEE Journal of Solid-State Circuits, vol. 56, no. 12, pp. 3668-3680, Dec. 2021 (ISSCC invited submission).
  8. Y. -C. Luo, A. Lu, J. Hur, S. Li and S. Yu, “Design and Optimization of Non-volatile Capacitive Crossbar Array for In-Memory Computing,” in IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 69, no. 3, pp. 784-788, Mar. 2022.
  9. Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun and David Z. Pan, “MAGICAL: An Open-Source Fully Automated Analog IC Layout System from Netlist to GDSII,” IEEE Design & Test, vol. 38, no. 2, pp. 19-26, Apr. 2021.
  10. Jiaxin Liu, Xiyuan Tang, Linxiao Shen, Shaolan Li, Zhelu Li, Wenjuan Guo, Nan Sun, “Error suppression techniques for energy-efficient high-resolution SAR ADCs,” Journal of Semiconductors, vol. 55, no. 11, Nov. 2020
  11. Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, and Nan Sun, “A 13.5-ENOB, 107-uW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 12, pp. 3248-3259, Dec. 2020 (ISSCC invited submission).
  12. Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, and Nan Sun, “An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter”, IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 11, pp. 3064-3075, Nov. 2020.
  13. Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, and Nan Sun, “A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 3, pp. 666-679, March 2020. (CICC invited submission).
  14. Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, and Nan Sun, “A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC),  Y. Zhong et al., “A Second-Order Purely VCO-Based CT $\Delta\Sigma$ ADC Using a Modified DPLL Structure in 40-nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 356-368, Feb. 2020.
  15. Shaolan Li, David Pan, and Nan Sun, “An OTA-less Second-Order VCO-based CT ΔΣ Modulator Using an Inherent Passive Integrator and Capacitive Feedback,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 5, pp. 1337-1350, May 2020.
  16. Linxiao Shen, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu, and Nan Sun, “A Two-Step ADC with a Continuous-Time SAR Based First Stage,” IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 12, pp. 3375-3385, Dec. 2019..
  17. Abhishek Mukherjee, Miguel Gandara, Biying Xu, Shaolan Li, Linxiao Shen, Xiyuan Tang, David Pan, and Nan Sun, “A 1 GS/s 20 MHz-BW Capacitive-Input Continuous Time ΔΣ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO,” IEEE Solid-State Circuits Letters (SSC-L), vol. 2, no. 1, pp. 1-4, Jan. 2019.
  18. Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, and Nan Sun, “Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs,” IEICE Transactions on Electronics, vol. 102, no. 7, pp. 509-519, July 2019. (invited)
  19. Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, and Nan Sun, “Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters,” IEEE Transactions on Circuits and Systems – I: Regular Papers (TCAS-I), vol. 66, no. 4, pp. 1342-1354, April 2019.
  20. Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, and Nan Sun, “A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer,” IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 2, pp. 428-440, Feb. 2019.
  21. Shaolan Li, Qiao Bo, Miguel Gandara, David Pan, and Nan Sun, “A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure,” IEEE Journal of Solid-State Circuits (JSSC ISSCC invited submission), vol. 53, no. 12, pp. 3484-3496, Dec. 2018.
  22. Shaolan Li, Abhishek Mukherjee, and Nan Sun, “A 174.3dB FoM VCO-Based CT ΔΣ Modulator with a Fully Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC ESSCIRC invited submission), vol. 52, no. 7, pp. 1940-1952, July 2017.

Conference

  1. Tian Xie, Ken Li, Tzu-Han Wang, Wei-En Lee, Engin Esen, Dong-Suk Kang, Shaolan Li, “An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping,” IEEE Custom Integrated Circuits Conference (CICC), 2024, accepted
  2. Wantong Li, Xitie Zhang, Junmo Lee, F. Levent Degertekin, Shaolan Li, Shimeng Yu, “Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator,”, IEEE Biomedical Circuits and Systems Conference (BIOCAS), 2023, accepted
  3. Xitie Zhang, Evren F. Arkan, Coskun Tekes, Tzu-han Wang, F. Levent Degertekin, Shaolan Li, “A 1.11 mm2 Guidewire IVUS SoC with +/- 50°-Range Plane Wave Transmit Beamforming,” IEEE European Solid-State Circuits Conference (ESSCIRC),  Lisbon, Portugal, 2023, pp. 309-312.
  4. Xitie Zhang, Evren F. Arkan, Coskun Tekes, Shaolan Li, F. Levent Degertekin, “Integrated System on a Chip for Guidewire IVUS,” IEEE International Ultrasonic Symposium (IUS), Venice, Italy, 2022, pp. 1-4
  5. Tzu-Han Wang*, Tian Xie*, Zhe Liu and Shaolan Li, “An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique, ” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb 2022*Equal contribution
  6. Y.-C. Luo, J. Hur, T.-H. Wang, A. Lu, S. Li, A. I. Khan, S. Yu, “Experimental demonstration of non-volatile capacitive crossbar array for in-memory computing,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec.2021.
  7. Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, and Nan Sun, “An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer,” IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr. 2021.
  8. Yuan-Chun Luo, Anni Lu, Jae Hu, Shaolan Li, and Shimeng Yu, “Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing,” International Memory Workshop (IMW), 2021, pp. 1-4.
  9. Tzu-Han Wang, Ruowei Wu, Vasu Gupta and Shaolan Li, “A 13.8-ENOB 0.4pF-CIN 3rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation”,  IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, Feb. 2021
  10. Shaolan Li, “A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, accepted.
  11. Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun and David Z. Pan, “GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance, ” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, Nov. 4-7, 2019. (accepted)
  12. Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, and Nan Sun, “A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF,” IEEE Symposium on VLSI Circuits (VLSI), Kyoto, Japan, Jun. 2019 .
  13. Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun and David Z. Pan, “WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout, ” ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun. 2-6, 2019.
  14.  Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan and Nan Sun, “A 0.025mm2 0.8V 78.5dB SNDR VCO-based Sensor Readout Circuit Using a Hybrid PLL-ΔΣM Structure, “, IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr. 14-17, 2019.
  15.  Shaolan Li, Biying Xu, David Z. Pan and Nan Sun, “A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library, “, IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr. 14-17, 2019.
  16. Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun and David Z. Pan, “Device Layer-Aware Analytical Placement for Analog Circuits, ” ACM International Symposium on Physical Design (ISPD), San Francisco, CA, Apr. 14-17, 2019. (Best Paper Award Finalist)
  17. Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, and Nan Sun, ”A 0.01mm2 25uW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor,” IEEE International Solid-State Circuits Conference (ISSCC), 2019.
  18. Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal Hall, Nan Sun, “A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter,” IEEE international Solid-State Circuits Conference (ISSCC), 2019.
  19. Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu and Nan Sun, “A Second-OrderPurely VCO-based CT ∆Σ ADC Using a Modified DPLL in 40-nm CMOS,” IEEE Asian Solid-State CircuitConference (ASSCC), Tainan, Taiwan, Nov. 2018.
  20. Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen and Nan Sun, “A 0.029mm^2 17-fJ/Conv.-Step CT Delta-Sigma ADC With 2nd-Order Noise-Shaping SAR Quantizer,” IEEE Symposium on VLSI Circuits (VLSI), June 2018, pp. 201-202.
  21. Arindam Sanyal, Shaolan Li, and Nan Sun, “Low-power Scaling-friendly Ring Oscillator based Delta-Sigma ADC,” IEEE International Symposium on Circuits and Systems (ISCAS invited), May 2018, pp. 1-5.
  22. Shaolan Li, Bo Qiao, Miguel Gandara, and Nan Sun, “A 13-bit ENOB 2nd-order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using an Error-Feedback Structure,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018, pp. 234 – 236
  23. Shaolan Li and Nan Sun, “A 0.028mm2 19.8fJ/step 2nd-Order VCO-based CT Delta Sigma Modulator Using an Inherent Passive Integrator and Capacitive Feedback in 40nm CMOS,” IEEE Symposium on VLSI Circuits (VLSI), pp. C36-C37, 2017.
  24. Biying Xu, Shaolan Li, Nan Sun, and David Z. Pan, “A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology,” IEEE Design Automation Conference (DAC), 2017.
  25. Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, and David Z. Pan, “Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits,” IEEE International Symposium on Physical Design (ISPD), 2017.
  26. Shaolan Li and Nan Sun, “A 174.3dB FoM VCO-Based CT ΔΣ Modulator with a Fully Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130nm CMOS,” IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 241-244, Sept. 2016.

Book Chapter

  1. Shaolan Li, Jiaxin Liu, Wenjuan Guo, and Nan Sun, “Noise-shaping SAR ADCs,” in Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits-Advances in Analog Circuit Design 2019, Springer, 2020, to appear.

Patents

  1. Levent Degertekin, Evren Arkan, Shaolan Li, Coskun Tekes, Xitie Zhang, “Improved Integrated Systems for Intravascular Ultrasound,” US Provisional Patent 63/378,926, 2022

Invited Talks

  1. “Harmonizing Energy Efficiency and Signal Chain Friendliness in High-Resolution ADCs,” Southern Methodist University, 05/3024
  2. “Harmonizing Energy Efficiency and Signal Chain Friendliness in High-Resolution ADCs,”  Texas A&M University, 03/3024
  3. “Fusing Performance and Productivity: New Design Strategies in Analog-to-Digital Converters,” University of Notre Dame, 02/2022
  4. “The Noise-Shaping SAR ADC: A Treasure Box Filled with Unconventional Capabilities,” Silicon Creation LLC, 10/2021
  5. “The Noise-Shaping SAR ADC: A Treasure Box Filled with Unconventional Capabilities,” Cirrus Logic, 08/2021
  6. “Towards “Plug-&-Play” Agile Analog Circuit Development: The Circuit-Level Approaches,” North Carolina State University ECE Colloquium, 11/2020.
  7. “Energy-Efficient Mixed-Signal Integrated Circuit Design in Advanced Technology Nodes,” Peking University, China, 05/2019.
  8. “Energy-Efficient Mixed-Signal Integrated Circuit Design in Advanced Technology Nodes,” Tsinghua University, China, 05/2019.
  9. “Energy-Efficient Mixed-Signal Integrated Circuit Design in Advanced Technology Nodes,” The University of Texas at Dallas, 03/2019.
  10. “Energy-Efficient Mixed-Signal Integrated Circuit Design in Advanced Technology Nodes,” Georgia Institute of Technology, 02/2019.
  11. “High-performance oversampling ADC design in advanced CMOS processes”, IEEE SSCS Dallas Chapter, 12/2018.